1. Field of the Invention
The invention relates to a digital information reproducing apparatus such as a magnetic disk apparatus or the like and relates to a reproducing method.
2. Description of the Related Art
In recent years, a maximum likelihood decoding system has frequently been used as a signal processing system which enables a high density recording. According to the maximum likelihood decoding system, maximum likelihood data is decoded at each time point while an amplitude level of a reproduction signal at a previous time point is referred to. If it has been known that the reproduction signal changes under some restriction, by knowing information regarding the reproduction signal at the previous time point, the decoding of higher precision than that in case of decoding by a bit-by-bit system can be performed.
In a PRML (Partial Response Maximum Likelihood) system which is a typical maximum likelihood decoding system and is constructed by a combination of a Viterbi decoding method and Partial Response, problems in the maximum likelihood decoding system will now be described hereinbelow with respect to PR1ML using, particularly, Partial Response Class 1 (hereinbelow, referred to as PR1) as an example.
An equalization signal which is obtained by PR1 equalization is also called PR(1,1). When xe2x80x9c1xe2x80x9d is inputted, an intercode interference of xe2x80x9c1xe2x80x9d occurs in the next bit. Therefore, two statuses (S0, S1) are determined in dependence on whether the just previous input value is equal to xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. An output value is, further, decided by the next input value in each of those statuses and the status is shifted to the next status. FIG. 10 shows an example of a rule of such a status transition. FIG. 11 is a trellis diagram showing a state of a status transition which can occur for one time point.
As a specific process to decide the status transition on the basis of the reproduction signal, the square of a difference between a reproduction signal level and a reference amplitude level (expected value) is calculated as follows at each time k. Calculation values which are obtained by such a method are referred to as branch metrics.
BM10=(Z(k)xe2x88x921)2xe2x80x83xe2x80x83(1)
BM11=(Z(k)xe2x88x922)2xe2x80x83xe2x80x83(2)
BM00=(Z(k)xe2x88x920)2xe2x80x83xe2x80x83(3)
BM01=(Z(k)xe2x88x921)2xe2x80x83xe2x80x83(4)
The equation (1) denotes a probability with respect to an assumption that the status S1 is shifted to the status S0. The equation (2) denotes a probability with respect to an assumption that the status S1 is shifted to the status S1. The equation (3) denotes a probability with respect to an assumption that the status S0 is shifted to the status S0. The equation (4) denotes a probability with respect to an assumption that the status S0 is shifted to the status S1.
As mentioned above, according to the maximum likelihood decoding system, maximum likelihood data is decoded at each time point while the amplitude level of the reproduction signal at the previous time point is referred to. For this purpose, the sum of the branch metrics until the status reaches the status S0 or S1 at each time point is stored. The sum of the branch metrics is called a path metric. In the actual decoding process, the value of the path metric is updated at each time k in accordance with the following calculations.
MT0k=min(MT0kxe2x88x921+BM00, MT1kxe2x88x921+BM10)xe2x80x83xe2x80x83(5)
MT1k=min(MT0kxe2x88x921+BM01, MT1kxe2x88x921+BM11)xe2x80x83xe2x80x83(6)
where, MT0k denotes a path metric of the status S0 at time k and MT0kxe2x88x921 denotes a path metric of the status S0 at time kxe2x88x921. Similarly, MT1k denotes a path metric of the status S1 at time k and MT1kxe2x88x921 denotes a path metric of the status S1 at time kxe2x88x921.
An arithmetic operating process according to the equation (5) is an operation for calculating probabilities of the path reaching S0 from S0 and the path reaching S0 from S1 for an interval from time kxe2x88x921 to time k and leaving the more probable path. An arithmetic operating process according to the equation (6) is an operation for calculating probabilities of the path reaching S1 from S0 and the path reaching S1 from S1 for an interval from time kxe2x88x921 to time k and leaving the more probable path.
At time k, when the path reaching S0 from S0 is selected by the arithmetic operating process according to the equation (5) and the path reaching S1 from S0 is selected by the arithmetic operating process according to the equation (6), it is determined that the status at time kxe2x88x921 is S0 and the statuses (paths) at all times before time kxe2x88x921 are determined. An example of the paths which are determined in this manner is shown by bold lines in FIG. 12. FIG. 12 shows an example of trellis diagrams among a plurality of time points.
A decoding apparatus for performing a maximum likelihood decoding has a construction to realize the foregoing processes. That is, the decoding apparatus has: a branch metric calculating circuit for calculating values of branch metrics in accordance with the equations (1) to (4); an ACS (Add Compare select) circuit for calculating the sum of a branch metric which is newly calculated at time k and the path metrics calculated until time kxe2x88x921 in accordance with the equations (5) and (6) and selecting the more probable path on the basis of a calculation value; and a path memory circuit for storing a value of the path metric at time point kxe2x88x921 which is used in the arithmetic operating process by the ACS at each time point k.
The ACS circuit will now be described in more detail hereinbelow in order to explain the problems in the maximum likelihood decoding. FIG. 13 shows an example of the ACS circuit. Two ACS circuits 100 and 200 perform the arithmetic operating processes according to the equations (5) and (6), respectively. In the arithmetic operating processes, an adding process, a comparing process, and a selecting process have to be performed as a series of processes for a period of time of one clock. In the ACS circuits 100 and 200, therefore, pipeline processes cannot be performed, it is also extremely difficult to perform parallel processes, and this results in a large obstacle in realization of a high processing speed of the Viterbi decoder.
As a recording modulating system, a (1,7) RLL (Run Length Limited) code in which: the number of xe2x80x9c0xe2x80x9d between xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d is limited to 1 or more and 7 or less, a (2, 7) RLL code in which the number of xe2x80x9c0xe2x80x9d between xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d is limited to 2 or more and 7 or less, or the like is known. According to those codes, since a shortest inverting interval Tmin is large, they are suitable for short wavelength recording. However, a clock rate rises (1.5 times, 2 times, respectively). Therefore, the combination of those recording modulating systems and the maximum likelihood decoding are improper to perform the recording and/or reproduction at a high speed.
It is an object of the invention to provide a digital information reproducing apparatus and a reproducing method which can solve the problems in the conventional techniques and perform the maximum likelihood decoding at a high speed.
According to one aspect of the invention, there is provided a digital information reproducing apparatus in which a digital reproduction signal that is reproduced from a recording media, and that is constructed by collecting Partial Response encoded signal portions each having a predetermined data amount is decoded by maximum likelihood decoding, comprising:
equalizing means for equalizing the digital reproduction signal by predetermined equalizing characteristics;
clock forming means for forming a first clock signal on the basis of an output of the equalizing means;
A/D converting means for A/D (analog/digital) converting the digital reproduction signal by the first clock signal;
time base decompressing means for performing a predetermined time base decompression to an output of the A/D converting means every signal portion by the first clock signal and a second clock signal which is supplied separately from the first clock signal and has a lower frequency than that of the first clock signal; and
maximum likelihood decoding means for outputting decoding data by performing a maximum likelihood decoding process to an output of the time base decompressing means,
wherein the digital reproduction signal is time base decompressed prior to maximum likelihood decoding the digital reproduction signal.
Further, in the digital information reproducing apparatus of the invention, the time base decompressing means is constructed by a plurality of time base decompressors, the maximum likelihood decoding means is also constructed by a plurality of maximum likelihood decoders connected to the time base decompressors, respectively, each of the time base decompressors sequentially time base decompresses one of division data of signal portions of the digital reproduction signals which is different from the other division data, and the maximum likelihood decoders perform the maximum likelihood decoding to an output of each of the time base decompressors connected to them.
According to another aspect of the invention, there is provided a digital information reproducing method in which a digital reproduction signal that is reproduced from a recording media, and that is constructed by collecting Partial Response encoded signal portions each having a predetermined data amount is decoded by maximum likelihood decoding, comprising:
an equalizing step of equalizing the digital reproduction signal by predetermined equalizing characteristics;
a clock forming step of forming a first clock signal on the basis of the equalized signal;
an A/D converting step of A/D (analog/digital) converting the digital reproduction signal by the first clock signal;
a time base decompressing step of performing a predetermined time base decompression to an output in the A/D converting step every signal portion by the first clock signal and a second clock signal which is supplied separately from the first clock signal and has a lower frequency than that of the first clock signal; and
a maximum likelihood decoding step of outputting decoding data by performing a maximum likelihood decoding process to an output in the time base decompressing step,
wherein the digital reproduction signal is time base decompressed prior to maximum likelihood decoding the digital reproduction signal.
According to the present invention, a data that is to be decoded is provided to the maximum likelihood decoding circuit after time base decompression is done. Therefore, operation rate of a decoding circuit is not to affect the operation rate of the whole circuits that performs decoding process.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.